Circuit designs, or circuit descriptions, are frequently specified using any of a variety of different software-based formats. For example, circuit descriptions can be specified using a hardware description language, such as VHDL or Verilog, or, in some cases, using a general-purpose, high-level programming language such as C++. Despite the particular manner in which a circuit design is specified, a user-created circuit description must undergo a significant amount of processing to generate a version of the circuit design that can be used to program a target device, i.e., a bitstream.
To physically implement a circuit design within a programmable logic device, such as a field programmable gate array (FPGA), for example, the circuit design must undergo various stages of processing such as synthesis, mapping, packing, etc. Each stage is typically performed by a design application, which may be included as part of an electronic design automation (EDA) system. The design applications usually operate sequentially, with each design application producing a different circuit description as output to be provided to the next design application, or stage, as input. For example, with respect to an FPGA, a user can first create a logical circuit description using an HDL. The logical circuit description is read by the design applications, with each design application transforming the circuit topology, connectivity, logical functions, etc. Each of the design applications creates a new circuit description that is saved to a file for use by the next design application in the implementation process.
Each of the circuit descriptions specifies circuit elements such as logic blocks, signals, pins, networks, etc. These circuit elements are modified or transformed as each application operates to produce a new circuit description output. The implementation process generates a series of independent circuit descriptions, with each circuit description reflecting the state of the circuit design in a different stage of the implementation process. The final processing stage produces a circuit description that specifies a set of building blocks, specific to the target device, which can be used to program the target device.
Another product of the implementation process that is generated by the design applications is correlation data. In general, correlation data specifies the transformations that are applied to the various circuit elements from one circuit description to the next. The correlation data effectively allows the design applications to determine associations between a given circuit element in one circuit description with circuit elements in one or more other circuit descriptions. That is, the correlation data indicates that a given circuit element, or set of elements, in one circuit description has been transformed into another element, or set of elements, or removed altogether, in another circuit description. For example, correlation data can indicate the particular logic gate circuit elements from one circuit description that have been combined into a particular Look-Up Table (LUT) circuit element in another circuit description.
The final circuit description can be analyzed to characterize the behavior of the circuit design. For example, reports can be created that provide the circuit designer with information about the validity and timing characteristics of an FPGA implementation. For this information to make sense to the circuit designer, the information must be presented in terms of the original user-specified circuit description, as it existed prior to any design implementation transformations. Correlation data permits analysis information corresponding to circuit elements of the final circuit description to be related to circuit elements of the user-specified circuit description, or any intermediate circuit description for that matter.
Correlation data also permits a user to specify implementation constraints at any time within the design implementation process. The implementation constraints can be specified with respect to the circuit elements of the user-specified circuit description. The correlation data can be used to apply, or map, those constraints to the proper circuit elements in the resulting circuit description or other intermediate circuit descriptions.
In known processes, correlation data is added to the circuit elements themselves, i.e., directly to the objects representing the circuit elements within each respective circuit description. Because correlation data is co-mingled with multiple circuit descriptions, determining relations between circuit elements of different circuit descriptions (for example, to track the transformation of a circuit element or group of circuit elements) can consume a significant amount of computing resources. In illustration, when correlation data is queried, an entire circuit description and accompanying correlation data is loaded into memory. A search is conducted within the circuit description to locate the desired circuit elements. The correlation data for those elements is accessed to identify any corresponding circuit elements in other circuit descriptions. Those circuit descriptions then can be loaded into memory and searched in an effort to locate further correlation data. The process continues to iterate until the query terminates. In view of the significant size of circuit descriptions and the need to load multiple circuit descriptions when executing a query, it can be seen that querying correlation data can be costly in terms of both time and system memory.
In addition to the high cost of searching correlation data, another disadvantage of co-mingling correlation data with circuit description data is that the likelihood of a design application corrupting a circuit element while trying to access correlation data is heightened. Any design application that works with the circuit description must be aware of the placement of the correlation data within the circuit description and take care not to delete, modify, or otherwise corrupt the correlation data or the circuit element objects.
The manner in which correlation data is maintained has been a disincentive to further development of design implementation functions that rely on correlation data. In light of the computational cost, many potential correlation functions are not implemented at all. It would be beneficial to provide a technique for managing correlation data for circuit design implementation in a manner that addresses the deficiencies described above.